In many clock recovery schemes used in transceivers, the timing recovery system uses a main analog element to control the recovered clock. For example, there is a voltage controlled oscillator (“VCO”) based clock generation where the VCO control signal is generated to track both the clock jitter as well as a constant clock offset between the initial VCO frequency and clock used by the remote transmitter.
Another method to recover the remote transmitter clock is to use a delta-sigma modulation (“DSM”) system to change the frequency of a provided clock source to track a remote clock system. For efficient design however, the tracking bandwidth of the DSM is limited. Another method is to use a phase interpolator based timing recovery system where the remote transmitter clock is recovered by passing a receiver clock source through different phase shifts such the PI clock output would be very close to the remote transmitted clock.
There are disadvantages to each approach however, as in very high speed communication systems where the timing error has to be very small (e.g. <0.5 picoseconds) the phase interpolator presents significant issues because of the integral nonlinearity (INL) and differential nonlinearity (DNL) of the phase-delay selection. The INL/DNL of the phase interpolator make it very challenging to compensate for a frequency offset between the local source and the remote transmitted clock. The DSM approach is limited by DSM loop BW. In high speed applications the TR loop bandwidth needs to be in the range of 1-50 MHz, which presents a very significant challenge for DSM type approaches
The above-described description is merely intended to provide a contextual overview of current techniques for providing power grid interfaces in a server on a chip and is not intended to be exhaustive.